The present invention relates to a method of fabricating a semiconductor device, and in particular to a semiconductor device employing a field effect transistor that operates at an ultra-high frequency band in the GHz (Giga Hertz) range.
Conventionally, a semiconductor device employing a field effect transistor (hereinafter, referred to as FET) that operates at an ultra-high frequency in the GHz range generally has a structure as shown in FIG. 13, for example. FIG. 13 is a pattern perspective view showing a conventional semiconductor device (an FET chip) when viewed from the top. At this semiconductor device, a plurality of unit FETs 200 are disposed in a line.
A unit FET 200 is provided on an active layer 202 formed on an underlying substrate. This unit FET 200 comprises a basic structure 100 having a source electrode 204, a drain electrode 206 and a gate electrode 208 (FIGS. 14A-14E). The gate electrode 208 is composed of an electrode section 208a and a gate finger 208b. The gate finger 208b is disposed between the source electrode 204 and the drain electrode 206. In addition, adjacent unit FETs 200 each share the source electrode 204 and the drain electrode 206. The gate finger 208b is continuous with the electrode section 208a, and the electrode section 208a is connected to a gate pad 212 that is a power supply point via a first contact hole 210 that penetrates an inter-layer insulating film formed on the gate electrode 208. The source electrode 204 is connected to a source pad 216 via a second contact hole 214 that penetrates an inter-layer insulating film formed thereon. The drain electrode 206 is connected to a first drain pad 220 via a third contact hole 218 that penetrates an inter-layer insulating film formed thereon. Further, this first drain pad 220 is connected to a second drain pad 224 on an air bridge wiring 222 formed so as to extend to the gate pad 212.
Now, a method of fabricating this semiconductor device will be described with reference to FIGS. 14A-14E. FIGS. 14A-14E are schematic views showing the structure in each of the main steps which are carried out to form a basic structure 100 of a unit FET.
First, a wafer that is a substrate 300 is provided. Then, an active layer 202 is formed by using an epitaxial growth or an ion implantation method on this substrate 300. Here, an n-type channel layer 302 and an n+ contact layer 304 are formed as the active layer 202. Next, a source electrode 204 and a drain electrode 206 that are two ohmic electrodes consisting of a metal made of three layers, i.e., AuGe, Ni, and Au layers are formed in an active region of the active layer 202 (FIG. 14A). Thereafter, an SiO2 mask having an opening is provided on the active layer region that includes these electrodes, and then, a region of the nxe2x88x92 contact layer 304 is etched by employing this mask. In this manner, a wide recess 306 that exposes a region of a part of the n-type channel 302 is formed such that a portion 304x of an n+ contact layer 304 remains (FIG. 14B). Thereafter, an SiO2 film is further formed at the upper side of the active layer that includes the inside of the wide recess 306, and an opening 308a having a smaller opening diameter than the above wide recess 306 is provided, thereby forming a mask 308. Etching is carried out by employing this mask 308, and a narrow recess 310 having a part of the n-type channel layer 302 removed therefrom is formed in the wide recess 306 (FIG. 14C). Next, a gate metal 312 is spatter-deposited on the entire surface, and is embedded in the narrow recess 310 (FIG. 14D). Subsequently, the gate metal 312 is processed so as to have the configuration of the gate metal 208 by employing dry etching, and then, the mask 308 of the SiO2 film is removed (FIG. 14E). In this manner, the basic structure 100 of the unit FET is obtained.
This basic structure is employed as a TEG-FET (Test Element Group-Field effect transistor), its characteristics are measured, and the characteristics of the finally obtained FET is predicted. Thereafter, an inter-layer insulating film is formed so as to cover the ohmic electrodes 204 and 206 and the gate electrode 208. Thereafter, first to third contact holes 210, 214, and 218 are formed at the inter-layer insulating film so as to expose the two ohmic electrodes 204 and 206 and the gate electrode 208. Next, a first wiring is formed so as to fill a contact hole. In this step of forming the first wiring, the source pad 216, first drain pad 220, second drain pad 224, and gate pad 212 shown in FIG. 13, are formed.
A part of the source pad 216 fills the second contact hole 214 that exposes a surface of the source electrode 204, and is connected to the source electrode 204. Similarly, a part of the first drain pad 220 fills the third contact hole 218 that exposes a surface of the drain electrode 206, and is connected to the drain electrode 206. In addition, a part of the gate pad 212 fills the first contact hole 210 that exposes the gate electrode 208, and is connected to the gate electrode 208. When a structure having this first wiring formed therein is viewed from the top in a planar manner, the first drain pad 220 and the second drain pad 224 are disposed at both sides while the gate pad 212 is sandwiched between these pads (FIG. 13).
After the first wiring has been formed, an air bridge wiring 222 that connects the first drain pad 220 and the second drain pad 224 to each other is formed as a second wiring. This air bridge wiring 222 is formed so as to encompass the gate pad 212, and the first and second drain pads 220 and 224 are connected to each other (FIG. 13).
Thereafter, a passivation film (not shown) is formed on the top surface of the structure.
A semiconductor device using the FET is formed by using the steps as has been described above.
In the semiconductor device with the above-described structure, the size of the FET, in particular, the gate width is determined by a width of the active region and the number of gate fingers. Therefore, the gate width depends on patterns of two masks; a mask employed for forming an active layer initially provided; and a mask for forming a gate electrode and a gate finger. When excess etching is carried out at the step of carrying out recess etching during the FET fabricating, for example, in an active region, the thickness of the active layer is reduced. Thus, there is a risk that a desired drain current value cannot be ensured. In contrast, in the case of insufficient etching, the thickness of the active layer is increased, and a drain current of equal to or more than the set value flows out.
Even if it is judged that an excess or shortage occurs with the drain current value by virtue of the aforementioned reason, as a result of measuring the characteristics of this TEG-FET, at a time when the basic structure 100 of the FET (TEG-FET) is formed, although a threshold voltage of the TEG-FET is a value within a desired range, this excess or shortage cannot be compensated for during the subsequent steps. Therefore, there is a risk that the FET cannot achieve its desired output characteristics. In addition, the FET having low output characteristics is faulty, and thus, there is a risk that the yield of a wafer lot is decreased.
The present invention provides a method of fabricating a semiconductor device that enables improvement of degraded characteristics after the characteristics of the TEG-FET has been measured.
In the present invention, when a semiconductor device having a structure in which a plurality of unit FETs are arranged in a line is fabricated, the number of the unit FETs in which a desired drain current value is obtained is first designed in advance. For example, this number is defined as xe2x80x98pxe2x80x99. Next, a number xe2x80x98mxe2x80x99 of basic structures of unit FETs are formed, where the number xe2x80x98mxe2x80x99 is more than xe2x80x98pxe2x80x99, the drain current value of each of these structure is measured, and the drain current value of the semiconductor device after being fabricated is predicted from this measured value. Thereafter, a predicted value and a desired drain current value are compared with each other, and the number xe2x80x98nxe2x80x99 of the semiconductor devices in which a desired drain current value is obtained is determined.
Here, the basic structure is defined as an element before being wired in which the source electrode, drain electrode, and gate electrode are formed on the region of the active layer. First, as long as xe2x80x98mxe2x80x99 (which is more than xe2x80x98pxe2x80x99) basic structures are formed, no shortage occurs with the drain current value of the semiconductor device to be fabricated. At a time when the basic structure is formed, a drain current value of each of the semiconductor devices to be obtained from the drain current value by each of the basic structures is predicted and this value is always greater than a desired value. Hence, the number of basic structures corresponding to a difference between the predicted value and the desired value is obtained, thereby making it possible to determine the number xe2x80x98nxe2x80x99 of the basic structures such that the minimum drain current value can be determined. Thus, even if any error occurs during the steps up until the basic structure has been formed, the number of the basic structures is adjusted, whereby the drain current value of the finally obtained semiconductor device can be set to a desired value. Therefore, at the step of wiring the basic structure which is to be carried out subsequently, a wiring pattern may be formed on xe2x80x98nxe2x80x99 basic structures. In this manner, a semiconductor device in which a desired drain current value is obtained can be fabricated with high yield.
The drain current value of one basic structure is measured, and the drain current value of the semiconductor device is predicted from this measured value. This predicted value is a value uniquely obtained by co-relating the measured drain current value to a characteristic chart. The chart shows a relationship between the drain current value by each of the basic structures at a time when the basic structure has been formed by employing the same fabricating method in advance and the drain current value of the semiconductor device after fabricated.
More specifically, this method of fabricating the semiconductor device preferably comprises the following steps of:
(1) forming xe2x80x98mxe2x80x99 active layer regions so as to be arranged in a line on the substrate, where the number xe2x80x98mxe2x80x99 is more than the number of unit FETs that have been designed;
(2) forming the gate electrode, source electrode, and drain electrode, respectively, on each region of xe2x80x98mxe2x80x99 active layer regions, thereby forming the basic structure of xe2x80x98mxe2x80x99 unit FETs;
(3) predicting a drain current value of the semiconductor device from the measured value obtained by measuring the drain current value by each of the basic structures, and comparing this predicted value and a desired drain current value, thereby determining the number xe2x80x98nxe2x80x99 of basic structures in which a desired drain current value is obtained;
(4) forming an inter-layer insulating film on the basic structure; and
(5) forming simultaneously a first contact hole that penetrates this inter-layer insulating film, and exposes a part of the surface of the gate electrode; a second contact hole that penetrates the inter-layer insulating film, and exposes a part of the surface of the source electrode; and a third contact hole that penetrates the inter-layer insulating film, and exposes a part of the surface of the drain electrode.
Forming the first to third contact holes, that is, the above step (5), is carried out for only a region on xe2x80x98nxe2x80x99 basic structures of the inter-layer insulating film, provided that mxe2x89xa7n and m, n greater than 0.
At a time when a basic structure of the unit FET is formed, when this basic structure is employed as a TEG-FET, thereby measuring a drain current value, the number xe2x80x98mxe2x80x99 of basic structures is more than the number of unit FETs that has been designed in advance. Thus, a higher value than a desired drain current value is obtained. In the case that the number of basic structures formed is the same as the number of FETs that has been designed in advance, if an error occurs during any of the steps of forming the basic structures, and a shortage occurs with the drain current value of the basic structure to be obtained, this shortage cannot be compensated for during the subsequent steps. As a result, the FET can not be presented as a product. In contrast, as described above, when the number of basic structures is more than the number of FETs that has been designed in advance, there is no risk that shortage occurs with the drain value of the basic structure. In the fabricating method according to the present invention, although the drain current value of the semiconductor device predicted from the drain current value of each of the basic structures is higher than a desired value, this value can be adjusted so that a desired value is obtained during the subsequent steps. The number of basic structures corresponding to the drain current difference between the predicted value and a desired value of the drain current is obtained, and the required number xe2x80x98nxe2x80x99 of basic structures in a structure being fabricated is determined. Hence, after the inter-layer insulating film has been formed on the basic structure, the step (5) of forming the first to third contact holes in the inter-layer insulating film so that a part of each basic structure is exposed, is carried out for only a region of the inter-layer insulating film on the determined xe2x80x98nxe2x80x99 basic structure. As a result, basic structures other than the xe2x80x98nxe2x80x99 basic structures are not elements that will operate in a semiconductor device to be fabricated. Hence, a semiconductor device in which desired drain current characteristics are obtained can be fabricated with high yield.
In addition, forming the first, second, and third contact holes in the region that corresponds to xe2x80x98nxe2x80x99 basic structure of xe2x80x98nxe2x80x99 inter-layer insulating films, i.e., the above step (5) is preferably carried out comprising the following the steps of:
(5-1) forming a resist film on the inter-layer insulating film;
(5-2) carrying out exposure and development for the resist film by employing a mask in which there are provided windows for forming contact holes that corresponds to the first to third contact holes to be formed in a region of the inter-layer insulating film of each of the basic structures,
wherein the (5-2) step is carried out by moving mask positions by a distance corresponding to that of one of the basic structures, to thereby form a resist pattern that has xe2x80x98nxe2x80x99 contact hole patterns;
(5-3) etching the inter-layer insulating film by employing a resist pattern formed by repeating the (5-2) steps xe2x80x98nxe2x80x99 times.
In this manner, first to third contact holes can be formed for exactly xe2x80x98nxe2x80x99 basic structures. In addition, even if desired drain current values are different, and the required number xe2x80x98nxe2x80x99 of basic structures varies, the aforementioned mask is for one basic structure, and therefore the same mask can be used regardless of the number of basic structures.
Another method of fabricating a semiconductor device having a structure in which a plurality of unit FETs are arranged in a line, as described above, comprises the 5 steps of:
(1) forming xe2x80x98mxe2x80x99 active regions on a substrate;
(2) forming a gate electrode, a source electrode, and a drain electrode on xe2x80x98mxe2x80x99 active layer regions, thereby forming a basic structure of the unit FET;
(3) determining the number xe2x80x98nxe2x80x99 of basic structures in which a desired drain current value is obtained;
(4) forming an inter-layer insulating film on a basic structure; and
(5) forming the first to third contact holes that correspond to xe2x80x98mxe2x80x99 basic structures on the inter-layer insulating film, the method further comprising the following 2 steps of:
(6) forming a gate pad in the first contact hole and on the inter-layer insulating film, forming a source pad in a second contact hole and on the inter-layer insulating film; forming a first drain pad in a third contact hole and on the inter-layer insulating film, and forming a second drain pad on the inter-layer insulating film, the pad being spaced apart from the first drain pad; and
(7) forming an air bridge wiring that connects the first and second drain pads to each other.
In addition, the pad forming step which is the above mentioned step (6) is carried out for the region on the xe2x80x98nxe2x80x99 basic structure on the inter-layer insulating film, provided that nxe2x89xa6m and 0 less than m and n.
The first contact hole exposes a part of the gate electrode, and thus, a gate pad formed in this first contact hole and on the inter-layer insulating film is electrically connected to a gate electrode. In addition, the second contact hole exposes a part of the source electrode, and thus, the source pad formed in this second contact hole and the inter-layer insulating film is electrically connected to the source electrode. In addition, the third contact hole exposes a part of the drain electrode, and the first drain pad formed in this third contact hole and on the inter-layer insulation layer is electrically connected to the drain electrode. Hence, materials which compose the gate pad, source pad, and first drain pad is not embedded in the contact hole formed respectively in the inter-layer insulating film on the basic structures other than xe2x80x98nxe2x80x99 basic structures, and thus, these pads, gate electrode, source electrode, and drain electrode are not electrically connected to each other, respectively. Therefore, in the semiconductor device to be fabricated, only xe2x80x98nxe2x80x99 unit FETs are effective FETs. Hence, a desired drain current value of the semiconductor device can be obtained. In addition, the drain pad connected to the drain electrode is composed of two pads, i.e., a first drain pad and a second drain pad. This is in view of the of a physical positional relationship which is taken into consideration for subsequent wiring on the inter-layer insulating film. The two pads are connected via an air bridge wiring. As long as this drain pad can be satisfactorily disposed as one pad on the inter-layer insulating film, it may be formed as one drain pad in a manner similar to the gate pad and the source pad. In addition, although the first drain pad and the second drain pad are connected to each other via an air bridge wiring, it is possible to make connection on the inter-layer insulating film via a general wiring. Air bridge wiring is preferably employed from the viewpoint of FET performance.
Preferably, the above pad forming step (6) further comprises the following steps of:
(6-1) forming a resist film on the inter-layer insulating film;
(6-2) forming a pad forming resist pattern to be developed after the resist film has been subjected to exposure by employing a pad pattern mask that has a pattern of the gate pad, source pad, first drain pad, and second drain pad; and a pad erasing mask that has a pattern configured so as to surround a predetermined pad forming region on basic structures other than non-xe2x80x98nxe2x80x99 basic structures; and
(6-3) forming the gate pad, source pad, first drain pad, and second drain pad by means of a lift-off method employing this pad forming resist pattern.
When a resist film is subjected to exposure by employing a pad pattern mask, a pattern latent image of regions for xe2x80x98mxe2x80x99 basic structures is formed on the resist film. When exposure is carried out by employing the pad erasing mask for this resist film, regions of the resist film that corresponds to basic structures other than xe2x80x98nxe2x80x99 basic structures, i.e., unwanted basic structures will remain after the image is developed. Hence, in the case where a negative resist is employed as a resist film, the pad erasing mask has windows that surround pad forming regions of basic structures other than xe2x80x98nxe2x80x99 basic structures. In addition, in the case where a positive resist is employed, there is employed a mask having a pattern such that the pad forming regions on the basic structures other than the xe2x80x98nxe2x80x99 basic structures are covered portions. As a result, the obtained pad forming resist pattern plays a role as a lift-off mask that can form pads on only regions of the inter-layer insulating film on the xe2x80x98nxe2x80x99 basic structures. When a material which composes a pad is vapor-deposited by this mask, the first to third contract holes formed each in the inter-layer insulating film on xe2x80x98nxe2x80x99 basic structures are filled, and the gate pad, source pad, first drain pad, and second drain pad are formed, respectively. Therefore, an unwanted basic structure, gate pad, source pad, and first drain pad are not electrically connected to each other. Thus, in the semiconductor device to be fabricated, the number of effective unit FETs is xe2x80x98nxe2x80x99. In this manner, a desired drain current value can be obtained.
Exposure of the aforementioned resist film is carried out by two-step exposure with first exposure employing a pad pattern mask and second exposure employing a pad erasing mask. In this manner, each of the pads that are electrically connected to the effective xe2x80x98nxe2x80x99 basic structures can be formed on these structures. In addition, the first and second exposures can obtain a pad forming resist pattern irrespective of which exposure is carried out first.
The step of forming a pad (6) may comprise the following sub-steps of:
(6-(1)) forming a resist film on an inter-layer insulating film;
(6-(2)) forming a pad forming resist pattern to be developed after the resist film has been developed by employing a pad pattern mask that has a pattern of the gate pad, source pad, first drain pad, and second drain pad; and a slit pattern mask that separates a region on xe2x80x98nxe2x80x99 basic structures and a region on non-xe2x80x98nxe2x80x99 basic structures; and
(6-(3)) forming the gate pad, source pad, first drain pad, and second drain pad by means of the lift-off method employing this pad forming resist pattern.
When a resist film is subjected to exposure by employing a pad pattern mask, a pattern latent image of the regions for xe2x80x98mxe2x80x99 basic structures is formed in the resist film. In addition, when a slit pattern mask is employed for this resist, if positioning is carried out on non-xe2x80x98nxe2x80x99 basic structures so that a slit pattern latent image is positioned between a region of xe2x80x98nxe2x80x99 basic structures and a region of non-xe2x80x98nxe2x80x99 basic structures, and then, exposure is carried out, the resist pattern obtained after being developed has a structure such that a pad pattern is divided into a pad pattern that covers the top of xe2x80x98nxe2x80x99 basic structures and a pad pattern that covers the top of basic structures other than the xe2x80x98nxe2x80x99 basic structures. In the case where a negative resist is employed as a resist film, a slit pattern mask is a mask in which a dividing portion is a window. In addition, in the case where a positive resist is employed as a resist film, a slit pattern mask is a mask in which a dividing portion is a covered portion. The thus obtained pad forming resist pattern includes two masks, i.e., a mask for forming each pad in the region of the inter-layer insulating film on xe2x80x98nxe2x80x99 basic structures and a mask for forming each pad in the region of the inter-layer insulating film on non-xe2x80x98nxe2x80x99 basic structures. Thereafter, when a material of which the pad is composed is vapor-deposited by employing this mask, the first to third contact holes formed respectively in the inter-layer insulating film on xe2x80x98nxe2x80x99 basic structures are filled, and the gate pad, source pad, first drain pad, and second drain pad are formed, respectively. In addition, on the unwanted basic structures other than the xe2x80x98nxe2x80x99 basic structures as well, the contact hole formed respectively in the inter-layer insulating film is filled, and each of the pads which are continuous with this film is respectively formed. However, since the region of xe2x80x98nxe2x80x99 basic structures is not electrically connected to that of the unwanted basic structures, xe2x80x98nxe2x80x99 unit FETs can be operated effectively in the semiconductor device to be fabricated. Hence, a desired drain current value is obtained. In addition, unwanted unit FETs can also be operated as FETs by applying a voltage to the gate pad, source pad, and drain pad. In this manner, instead of adjusting the number of unit FETs in order to obtain a desired drain current value, a dividing position is selected or a plurality of parts are divided, thereby making it possible to determine the gate width dependency of the FET characteristics in one FET chip.
In addition, exposure of the aforementioned resist film is carried out by a two-step exposure with the first exposure employing a pad pattern mask and the second exposure employing a slit pattern mask. In this manner, each of the pads that are electrically connected to these structures can be formed on effective xe2x80x98nxe2x80x99 basic structures. Even on unwanted basic structures, each pad can be formed each in a state in which each pad is electrically disconnected from the pad formed on the xe2x80x98nxe2x80x99 basic structures. Either of the first and second exposures may be performed first.
A method that differs from the above two methods of fabricating a semiconductor device having a structure in which a plurality of unit FETs are arranged in a line comprises the following steps.
First, as in the steps (1) and (2) of the above two methods, the basic structure of the unit FET is formed on xe2x80x98mxe2x80x99 active layer regions formed on the substrate. This method further comprising the steps of:
(III) dividing xe2x80x98mxe2x80x99 basic structures by xe2x80x98xxe2x80x99 unit FET blocks composed of a plurality of basic structures, thereby determining the number xe2x80x98yxe2x80x99 of unit FET blocks in which a desired drain current value is obtained;
(IV) forming an inter-layer insulating film on the xe2x80x98xxe2x80x99 unit FET blocks;
(V) forming the first to third contact holes that correspond to xe2x80x98mxe2x80x99 basic structures on the inter-layer insulating film;
(VI) forming a gate pad in the first contact hole and on the inter-layer insulating film in unit FET blocks, forming a source pad in the second contact hole and on the inter-layer insulating film in unit FET blocks, forming a first drain pad in the third contact hole and on the inter-layer insulation pad, thereby forming the second drain pad in unit FET blocks on the inter-layer insulating film, the second drain pad being spaced apart from the first drain pad; and
(VII) forming a wiring between the first pads that connects a first drain pad and a second drain pad to each other, and forming a wiring between the second pads for coupling xe2x80x98yxe2x80x99 gate pads of the xe2x80x98xxe2x80x99 pads, source pads, and second drain pads, respectively,
provided that the above xe2x80x98xxe2x80x99 and xe2x80x98yxe2x80x99 are 0 less than m, 0 less than x, y less than m, and y less than x.
In this manner, xe2x80x98xxe2x80x99 unit FET blocks having at least two unit FETs are formed. xe2x80x98yxe2x80x99 unit FET blocks of the xe2x80x98xxe2x80x99 blocks are electrically connected through a wiring between the second pads. In the semiconductor device to be fabricated, thus, each of the FETs in these xe2x80x98yxe2x80x99 unit FET blocks can be effectively operated. In addition, in the unwanted unit FET blocks of the xe2x80x98xxe2x80x99 blocks as well, the gate pad, source pad, and drain pad are formed, and therefore, a voltage is applied to each of these pads, whereby the pads can be operated as FETs. Hence, instead of adjusting the number of unit FET blocks in order to obtain a desired drain current value, a number of electrically connected FETs which employ this adjustment method and have varying numbers of blocks are formed, thereby making it possible to determine the gate width dependency of the FET characteristics in one FET chip.
By electrically connecting xe2x80x98yxe2x80x99 unit FET blocks of the xe2x80x98xxe2x80x99 blocks through wiring between the second pads, each pad is formed by each unit FET block, and then, a resist film is formed on this structure. Then, the two-step exposure is carried out by exposure employing a mask having a wiring pattern in which the wire connects the first pads to each other and a mask having a wiring pattern in which the wire connects the second pads to each other and with exposure employing a mask having a pattern for erasing wiring in which the erasing wiring connects the second pads of unit FET blocks other than xe2x80x98yxe2x80x99 unit FET blocks to each other. Subsequently the resist film which is formed is developed, and a resist pattern is thereby formed. Then, after a wiring material has been vapor-deposited on the resist pattern, the resist pattern is removed. In this manner, the pads in xe2x80x98yxe2x80x99 unit FET blocks can be connected to each other. In addition, the first pad wiring between the first drain pad and the second drain pad is formed. This first pad wiring may be air bridge wiring. In this case, for example, a resist pattern is formed between the first drain pad and the second drain pad so as to be a pillow. Next, the first drain pad and the second drain pad are provided via the top surface of the pillow, and a wiring material is formed. Thereafter, the above resist pattern is removed, and an interval between the first drain pad and the second drain pad can thereby be bridged by the first pad wiring without being brought into contact with another region between the first and second drain pads.
As is evident from the foregoing description, according to the method of fabricating the semiconductor device of the present invention, the number of the unit FETs in which a desired drain current value is obtained is first designed in advance. This fabricating method comprises the steps of:
(1) forming xe2x80x98mxe2x80x99 active layer regions more than the number of the designed unit FETs so as to be arranged in a line on a substrate;
(2) the step for forming a gate electrode, a source electrode, and a drain electrode, respectively, on each region of the xe2x80x98mxe2x80x99 active layer regions, thereby forming a basic structure of xe2x80x98mxe2x80x99 unit FETs;
(3) predicting a drain current value of the semiconductor device from the value obtained by measuring the drain current value of each of the basic structures, and comparing this predicted value with a desired drain current value, thereby determining the number xe2x80x98nxe2x80x99 of basic structures in which a desired drain current value is obtained;
(4) forming an inter-layer insulating film on the basic structure; and
(5) simultaneously forming a first contact hole that penetrates this inter-layer insulating film to expose a part of the surface of the gate electrode; a second contact hole that penetrates the inter-layer insulating film to expose a part of the surface of the source electrode; and a third contact hole that penetrates the inter-layer insulating film to expose a part of the surface of the drain electrode.
Forming the first to third contact holes, that is step (5), is carried out for only a region on xe2x80x98nxe2x80x99 basic structures of the inter-layer insulating film, provided that mxe2x89xa7n and m, n greater than 0.
At a time when a basic structure of the unit FET is formed, when this basic structure is employed as a TEG-FET, thereby measuring a drain current value, the number xe2x80x98mxe2x80x99 of the basic structures is more than the number of the unit FETs that has been designed in advance. Thus, a drain current value higher than a desired drain current value is obtained. In the case where the number of basic structures is the same as the number of FETs that has been designed in advance, if an error occurs in any of the steps of forming a basic structure, shortage occurs with the drain current value of the obtained basic structure, and this shortage cannot be compensated for during the subsequent steps. As a result, the basic structure cannot be produced as a FET. In contrast, as described above, when the number of basic structures is more than the number of FETs that has been designed in advance, there is no risk that shortage occurs with the drain current value of the basic structure. In the fabricating method according to the present invention, although the drain current value of the semiconductor device predicted from the drain current value by each of the drain current value of the basic structure is higher than a desired value, this value can be adjusted to be a desired value during the subsequent steps. The required number xe2x80x98nxe2x80x99 of basic structures in the structures being fabricated is determined based on the predicted value and desired value of the drain current. Hence, the step (5) of forming an inter-layer insulating film on a basic structure, and then, forming the first to third contact holes so that a part of each basic structure is subjected to exposure to the inter-layer insulating film is carried out for only a region of the inter-layer insulating film on the determined xe2x80x98nxe2x80x99 basic structures. In this manner, non-xe2x80x98nxe2x80x99 basic structures are not elements that operate in the semiconductor device to be fabricated. Hence, the semiconductor device in which desired drain characteristics are obtained can be fabricated with high yield.